ISE调用modelsim进行前仿真的问题
时间：10-02
整理：3721RD
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ISE调用modelsim进行前仿真时的出现以前错误，代码中调用了FIFO的IP核。期待高手解答，不胜感激
# Loading work.tt
# Loading work.test_FIFO
# Loading work.test_FIFO_IP
# ** Error: (vsim-3033) ../scr/test_FIFO_IP.v(157): Instantiation of 'FIFO_GENERATOR_V4_4' failed. The design unit was not found.
# Region: /tt/uut/test_FIFO_IP
# Searched libraries:
# C:\Modeltech_xe_starter\xilinx\verilog\xilinxcorelib_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unisims_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unimacro_ver
# E:\test_FIFO_IP_1\test\work
# Loading work.glbl
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./tt.fdo PAUSED at line 9
# Loading work.tt
# Loading work.test_FIFO
# Loading work.test_FIFO_IP
# ** Error: (vsim-3033) ../scr/test_FIFO_IP.v(157): Instantiation of 'FIFO_GENERATOR_V4_4' failed. The design unit was not found.
# Region: /tt/uut/test_FIFO_IP
# Searched libraries:
# C:\Modeltech_xe_starter\xilinx\verilog\xilinxcorelib_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unisims_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unimacro_ver
# E:\test_FIFO_IP_1\test\work
# Loading work.glbl
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./tt.fdo PAUSED at line 9
在simulation时vsim work.(name)_tb.v work.glbl.v
两个一起仿真
应该是库没有编译好吧
应该是库没有编译好吧
没有把库加载好
呵呵，是库文件没编译，以下是我的解决办法 点到仿真模式，在source里面选中你建立工程选择的芯片，然后看Processes，点开，有个compile HDL simulation library，运行一下就OK了”
学习 啊
要是调用IPCore，一定要先编译库，要是代码简单且全为行为描述，就可以不用编译库了。
Xilinx的库没编译过去
\Xinlinx\ISE\bin\ntcompxlib.exe
学习学习