看看我的第一个设计的资源利用情况。
时间：10-02
整理：3721RD
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用的是xc2s100fg256-6
是一个数字钟，有计时，闹钟，跑表，整点报时的功能。输出是7段数码管。
但是用synplify和XST综合后的差别很大。并且请大家看看用了这些资源是不是正常。
synplify综合后map的报告：
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Total Number Slice Registers: 166 out of 2,400 6%
Number used as Flip Flops: 165
Number used as Latches: 1
Number of 4 input LUTs: 395 out of 2,400 16%
Logic Distribution:
Number of occupied Slices: 256 out of 1,200 21%
Number of Slices containing only related logic: 256 out of 256 100%
Number of Slices containing unrelated logic: 0 out of 256 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 410 out of 2,400 17%
Number used as logic: 395
Number used as a route-thru: 15
Number of bonded IOBs: 38 out of 176 21%
Number of GCLKs: 4 out of 4 100%
Total equivalent gate count for design: 3,962
Additional JTAG gate count for IOBs: 1,824
Peak Memory Usage: 63 MB
XST综合后map的报告：
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 197 out of 2,400 8%
Number of 4 input LUTs: 483 out of 2,400 20%
Logic Distribution:
Number of occupied Slices: 334 out of 1,200 27%
Number of Slices containing only related logic: 334 out of 334 100%
Number of Slices containing unrelated logic: 0 out of 334 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 550 out of 2,400 22%
Number used as logic: 483
Number used as a route-thru: 67
Number of bonded IOBs: 36 out of 176 20%
IOB Flip Flops: 3
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 2 out of 4 50%
Total equivalent gate count for design: 5,059
Additional JTAG gate count for IOBs: 1,824
Peak Memory Usage: 63 MB
差距咋这么大呢?：）
是一个数字钟，有计时，闹钟，跑表，整点报时的功能。输出是7段数码管。
但是用synplify和XST综合后的差别很大。并且请大家看看用了这些资源是不是正常。
synplify综合后map的报告：
Design Summary
--------------
Number of errors: 0
Number of warnings: 1
Logic Utilization:
Total Number Slice Registers: 166 out of 2,400 6%
Number used as Flip Flops: 165
Number used as Latches: 1
Number of 4 input LUTs: 395 out of 2,400 16%
Logic Distribution:
Number of occupied Slices: 256 out of 1,200 21%
Number of Slices containing only related logic: 256 out of 256 100%
Number of Slices containing unrelated logic: 0 out of 256 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 410 out of 2,400 17%
Number used as logic: 395
Number used as a route-thru: 15
Number of bonded IOBs: 38 out of 176 21%
Number of GCLKs: 4 out of 4 100%
Total equivalent gate count for design: 3,962
Additional JTAG gate count for IOBs: 1,824
Peak Memory Usage: 63 MB
XST综合后map的报告：
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Logic Utilization:
Number of Slice Flip Flops: 197 out of 2,400 8%
Number of 4 input LUTs: 483 out of 2,400 20%
Logic Distribution:
Number of occupied Slices: 334 out of 1,200 27%
Number of Slices containing only related logic: 334 out of 334 100%
Number of Slices containing unrelated logic: 0 out of 334 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 550 out of 2,400 22%
Number used as logic: 483
Number used as a route-thru: 67
Number of bonded IOBs: 36 out of 176 20%
IOB Flip Flops: 3
Number of GCLKs: 2 out of 4 50%
Number of GCLKIOBs: 2 out of 4 50%
Total equivalent gate count for design: 5,059
Additional JTAG gate count for IOBs: 1,824
Peak Memory Usage: 63 MB
差距咋这么大呢?：）
[讨论]看看我的第一个设计的资源利用情况。
这个本来就是synplify的强项啊。
[讨论]看看我的第一个设计的资源利用情况。
个人认为还是不要采用XST综合。曾经参加研讨会，有人说XST好，因为XILINX更了解它自己的期间结构。但我认为，综合效果的好坏与综合算法关系最大，这一点XILINX肯定不如synplicity了。
Synplify,Amplify,Precision都还不错。
非常好用！
好，谢谢！
支持~