微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 我运行仿真是出的错误谋求高人指点啊~

我运行仿真是出的错误谋求高人指点啊~

时间:10-02 整理:3721RD 点击:
Reading C:/modeltech_6.5/tcl/vsim/pref.tcl
# 6.5
# do elements_8_3rd_time_sequence.ado
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module elements_8_3rd_time_sequences
#
# Top level modules:
#  elements_8_3rd_time_sequences
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module elements_8_3rd_time_sequence
#
# Top level modules:
#  elements_8_3rd_time_sequence
# Model Technology ModelSim SE vlog 6.5 Compiler 2009.01 Jan 22 2009
# -- Compiling module glbl
#
# Top level modules:
#  glbl
# vsim -L uni9000_ver -lib work -t 1ps elements_8_3rd_time_sequence glbl
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: (vopt-19) Failed to access library 'uni9000_ver' at "uni9000_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: elements_8_3rd_time_sequence.ant(164): Library uni9000_ver not found.
# ** Warning: Unable to find library 'uni9000_ver'.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Executing onElabError command(s): resume
# ** Error: No Design Loaded!
# Executing ONERROR command at macro ./elements_8_3rd_time_sequence.ado line 14
ERROR: VSim failed to simulate annotated testbench

仿真库没连接上 重新连接一下

# ** Note: (vsim-3812) Design is being optimized...
先建议你simulate窗口的优化的那个勾去掉

恩,库没连接好,又连了一遍~成功了~

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top