任何对SRLC16E元件进行声明？
时间：10-02
整理：3721RD
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SRLC16E_inst : SRLC16E
-- The following generic declaration is only necessary if you
-- wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q, -- SRL data output
Q15 => Q15, -- Carry output (connect to next SRL)
A0 => A0, -- Select[0] input
A1 => A1, -- Select[1] input
A2 => A2, -- Select[2] input
A3 => A3, -- Select[3] input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRLC16E_inst instantiation
看到手册上对于SRLC16E元件例化使用如上的方法，请问该怎么声明呢 ?也就是这里的 INIT在声明的时候应该用什么类型呢 ?
-- The following generic declaration is only necessary if you
-- wish to change the initial.
-- contents of the SRL to anything other than all zero's.
generic map (
INIT => X"0000")
port map (
Q => Q, -- SRL data output
Q15 => Q15, -- Carry output (connect to next SRL)
A0 => A0, -- Select[0] input
A1 => A1, -- Select[1] input
A2 => A2, -- Select[2] input
A3 => A3, -- Select[3] input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRLC16E_inst instantiation
看到手册上对于SRLC16E元件例化使用如上的方法，请问该怎么声明呢 ?也就是这里的 INIT在声明的时候应该用什么类型呢 ?
component SRLC16E
generic (INIT : bit_vector := X"0000");
port (
D : in std_logic;
CE : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic;
Q15 : out std_logic);
end component;
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