微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > 关于EPM7128SI/O口多电平配置的问题?

关于EPM7128SI/O口多电平配置的问题?

时间:10-02 整理:3721RD 点击:
小弟第一次使用CPLD,问各位大哥一个问题:
7128S支持I/O口的多电平,我现在要用3.3V和5V,但是不知道那几个引脚与那个VCCIO之间对应?
希望哪位XD帮忙解答一下!

you'd need to refer to the datasheet for this kind of information.
typically, there're something called "io banks".  Inside the pad ring, each io banks can have a seperate io voltag.  Just search for bank in the respective datasheet.

I have read the datasheet!
but i didn't find the information about the I/O port or banks!

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top