两个fpga板高速通信问题

不好意思，把发往英文网站的问题直接贴到这里了，希望各位不要介意哦
I'm trying to work on communication between two board A and B equipped with FPGA,440 bits data must be transfered from A to B in 3 us,
there are three lines for communication.In addition,there are 8 A boards must communicated with B simutaneously, I use DS coding to transmit,
which works at 200MHZ for communication of one A and B,but when it comes to communication of  8 A and B,it doesn't work even at 100MHZ,probably
it's because crosstalk.I don't know how to solve this problem?Anybody has solution?Perhaps I can change the way of communication,but what else
communication protocol can I use? I don't have many experiences about design of FPGA,can anybody help me to work this problem out,any suggestion
is appreciated.
PS,board A contains virtex2,board B contains virtex4,so SERDES is not suitable here.
board A has only virtex2,nothing else processor.
board B has only virtex4,nothing else processor.

期待着高手解答

Re: problem with high speed data transfer
这是英文论坛里别人的回复和我的答复，我直接转到这里了
Gabor
Thank you for the reply.I'm sorry I didn't describe it clearly.
--What about data from B to A?
No data should be transferred from B to A.
--If not can you use LVDS for the interconnect?
Yes,I use LVDS for the interconnect .
If Virtex2 is the source, you can use DDR flops to drive the interface.
I will have a look at DDR flops.
--What makes you think the problem is crosstalk? Do you have adequate
--grounding on the cables?
I just think it should be crosstalk,because 8 links work at the high speed at the same time.The cables are network cables,which are not grounded.
--Are you using DCI or series resistors at the driver to reduce overshoot?
No,I didn't use any DCI or resistros.Can ou get a single link to work
reliably?
I just did the test in only B board,which means B sends and B receives it back.
For one link,it workes reliably.
But for more than one link,it doesn't work,the received data is wrong.when I do post simulation in questasim,more than one links receiver have unknown state.even if I reduce the speed to 100 MHZ,I don't know why.

高手帮忙翻译一下吧

FPGA时序分析之Gated Clock 1 » 发表回复

翻译成中文吧

采用DDR
正确端接
同步是个问题，用DCM同步两个FPGA
可能需要用IDELAY 调整延时，这样可以采样到正确的信号

dddddddddddddddddd

看不明白你写的
你用LVDS不错，你同是时用LVDS传送时钟吗，还是用ROcketIO之类的如恢复时钟。

这个问题很有深度的说

关注,MARK.

应该需要一个握手