过BUFG的信号没有走全局时钟。不理解。求高人解答

WARNINGarHelpers:79 - The following Clock signals are not routed on the dedicated global clock routing resources. This will usually result in longer delays and higher skew for the clock load pins. This could be the result of incorrect clock placement, more than 8 clocks feeding logic in a single quadrant of the device, or incorrect logic partitioning into the quadrant(s). Check the timing report to verify the delay and skew for this net
Net Name: sClk_27M
用的是VC2P7, sClk_27M过bufg, 但是在 PAR 报告里产生了上述警告，没太看明白，求高手解惑。