有人知道在时序分析器中看到的Tsrck什么意思吗，为什么在data sheet中找不到

来自于Viretex-4 FPGA User Guide的一句话
Tsrck/Tcksr:Time before Clock(CLK) that the SR (Set/Reset) and the BY(Rev) inputs of the slice must be stable at the SR/Rev-inputs of the slice sequential elements(configured as a flip-flop).Synchronous set/reset only.
附图说明为：
At time Tsrck before clock event(3), the SR signal(configured as synchronous reset in this case) becomes valid-high, resetting the slice register.This is reflected on the XQ or YQ pin at time Tcko after clock event(3).

Tsrck

希望对你有用

谢谢，真是我所想要的，我的PROJECT是建立在V2P上的，所以查不到