how to generate memory？

hi, everyone
there are 2 questions about memory.
1  in general, an off-chip rom or ram is only generated for simulation, and neednot to be synthesized.
    the question is if u need to synthesize an on-chip ram or register file, or generate it with the help of "Memory Compiler" as in question 2.
2  as i know, the memory is generated with "Memory Compiler".
           1) Memory Compiler -> *.lib
           2) Library Compiler:  *.lib -> *.db
           3) *.db as a "link_library" of DC
    my question is when u synthesize ur deisgn, the corresponding code "memory.v" in ur design looks like the desciption below,or other forms,or neednot a memery verilog at all ?
             module memory(... );
                input ...;     
                output ...;   
                  always @(posedge clk)
                    if (memwrite_en == 1)
                        memory[write_add] <= write_data;
                assign  read_data =  memory[read_add];
            endmodule
SOS！
and every advice will be appreciated.
sevid

你的memory模块只需要verilog定义端口信息，DC综合时设为模块dont touch，其余的都是后端处理

When you want to generate  correct memory  upon your verilog code, you must write the verilog code  according to the description forms that be refered in the manual.
you should have a reset singal in your verilog description above.   
in FPGA design , you can choose to synthesis the memory to regs or implement  it with the memory in FPGA.

看到有些自己生成的memory 形如:TS1GE1024X16M4.v 的文件，不清楚这些文件是怎么样得来的，有哪位朋友知道或者听说过吗? 不防和大家分享一下对这些文件的理解、由来  Thanks！