求助VHDL程序（急）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library synplify;
use synplify.attributes.all;
entity blockdram is
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
end blockdram;
architecture arch_blockdram of blockdram is
type ram_memtype is array (depth-1 downto 0) of std_logic_vector
(Dwidth-1 downto 0);
signal mem : ram_memtype := (others => (others => '0'));
attribute syn_ramstyle of mem : signal is "block_ram";
signal addrb_reg: std_logic_vector(Awidth-1 downto 0);
begin
wr: process( clka )
begin
  if rising_edge(clka) then
   if wea = '1' then
    mem(conv_integer(addra)) <= dia;
   end if;
  end if;
end process wr;
rd: process( clkb )
begin
  if rising_edge(clkb) then
   addrb_reg <= addrb;
  end if;
    end process rd;
dob <= mem(conv_integer(addrb_reg));
end arch_blockdram;
红色字体出现错误，请问是什么原因，我用的是Modelsim

报错的信息是怎么说的?看样子是你的library它找不到啊.

你没有加入syniplify的库，当然要报错了！

找不到这个库

牛啊帅哥,想不到的强帖
牛啊帅哥,想不到的强帖






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汽车电子狗

syniplify的库怎么加的啊，高手指点下，谢谢

这个问题很简单，我只是奇怪，这段代码是RAM仿真模型，为什么要调用Synplify的库?
Synplify只是综合工具，不应该和仿真库有交集啊?

进来看看
进来看看；；