ise 综合错误 Xst:1710
时间：10-02
整理：3721RD
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verilog代码如下：
module DataProcess(rst_n,sig_0,in,out,sig_1,clk);
input rst_n;
input sig_0,clk;
input [23:0]in;
reg [511:0]data;
reg[511:0]temp;
reg[2:0] a;
parameter IDLE=3'b000,START=3'b001,PROCESS=3'b010,DONE=3'b100;
output reg[511:0] out;
output reg sig_1;
integer j;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
data (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
求问各位大神怎么解决
module DataProcess(rst_n,sig_0,in,out,sig_1,clk);
input rst_n;
input sig_0,clk;
input [23:0]in;
reg [511:0]data;
reg[511:0]temp;
reg[2:0] a;
parameter IDLE=3'b000,START=3'b001,PROCESS=3'b010,DONE=3'b100;
output reg[511:0] out;
output reg sig_1;
integer j;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
data (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
求问各位大神怎么解决
已经知道问题了，是input的输入的值的问题，谢谢大家