编译时提示产生了lacth请问怎么解决?
时间:10-02
整理:3721RD
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写了一个小程序,仿真可以通过但烧到板子上运行不正常,看了一下编译过程发现CW和NCW两个信号产生了LATCH,请问有知道是为什么的吗?如何解决呢?
代码如下:
--*****************************************************
-- Filename :
-- Author :
-- Description :
-- Callde by :
-- Revision : R1.0
-- Date :
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;
entity encoder is
port (
--------------ROTARY INPUT --------------
PI_A : in std_logic;
PI_B : in std_logic;
RESET : in std_logic;
CLK : in std_logic;
--------------SWITCH CONTROL--------------
PO_CW : out std_logic :='0'; --CW FOR CLOCKWISE;
PO_NCW : out std_logic :='0' --nCW FOR ANTICLOCKWISE;
);
end encoder;
architecture behav of encoder is
--------------SIGNAL DEFINE--------------
type state_type is (s00,s01,s10,s11);
signal PR_STATE, NT_STATE :state_type;
signal CW,NCW :std_logic;
signal CLK_CNT1 : std_logic_vector(15 downto 0) :="0000000000000001";
signal CLK_CNT2 : std_logic_vector(15 downto 0) :="0000000000000001";
begin
process(CLK,RESET)
begin
if(RESET = '1') then
PR_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE '0');
PO_CW '0');
PO_NCW
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE '0');
PO_CW '0');
PO_NCW <= '0';
else
CLK_CNT2 <= CLK_CNT2+1;
end if;
end if;
if (NCW = '1') then
CLK_CNT2 <= "0000000000000000";
PO_NCW <= '1';
end if;
end process;
end behav;
就可以了。
代码如下:
--*****************************************************
-- Filename :
-- Author :
-- Description :
-- Callde by :
-- Revision : R1.0
-- Date :
--*****************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all ;
use IEEE.std_logic_unsigned.all ;
entity encoder is
port (
--------------ROTARY INPUT --------------
PI_A : in std_logic;
PI_B : in std_logic;
RESET : in std_logic;
CLK : in std_logic;
--------------SWITCH CONTROL--------------
PO_CW : out std_logic :='0'; --CW FOR CLOCKWISE;
PO_NCW : out std_logic :='0' --nCW FOR ANTICLOCKWISE;
);
end encoder;
architecture behav of encoder is
--------------SIGNAL DEFINE--------------
type state_type is (s00,s01,s10,s11);
signal PR_STATE, NT_STATE :state_type;
signal CW,NCW :std_logic;
signal CLK_CNT1 : std_logic_vector(15 downto 0) :="0000000000000001";
signal CLK_CNT2 : std_logic_vector(15 downto 0) :="0000000000000001";
begin
process(CLK,RESET)
begin
if(RESET = '1') then
PR_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE '0');
PO_CW '0');
PO_NCW
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE
if(PI_A='1' and PI_B='0') then
NT_STATE
if(PI_A='0' and PI_B='0') then
NT_STATE '0');
PO_CW '0');
PO_NCW <= '0';
else
CLK_CNT2 <= CLK_CNT2+1;
end if;
end if;
if (NCW = '1') then
CLK_CNT2 <= "0000000000000000";
PO_NCW <= '1';
end if;
end process;
end behav;
就可以了。
学习了很多,谢谢
发完帖子就找到了解决办法,在case语句之前分别给cw和ncw赋值为0就可以了,
基本功能就是解码光电编码器的输出,来产生正转和反转两个脉冲,问题已经解决,是cw和ncw没有赋初值造成的
怎么把这1积分给你?