Design Challenges for an Ultra

Conclusion

The 100fs jitter target at 2GHz proved harder to attain than originally anticipated. Data indicate that it can be achieved using a fairly standard PLL circuit. The key design components are the VCO and the reference oscillator. UMX proved to have VCOs with best-in-class phase-noise performance. The remaining two hurdles are: (1) selecting a reference oscillator with sufficiently low noise; and (2) selecting an appropriate gain amplifier. Fortunately, there are many sources of these components, so a good strategy will plan the initial layout to include several different popular footprints. The gain amplifier is more difficult; further analysis will determine whether it can be placed within the loop and what noise impact it will have.