Design Challenges for an Ultra

Schematic for the Synthesizer

Figure 5 shows the complete circuit schematic for which the reference oscillator and VCO have already been discussed. The PLL is a Fujitsu? MB15E06SR with integrated 4mA charge pump and a maximum prescaler frequency of 3GHz. The PLL has to be programmed, so an ultra-simple PIC microcontroller with built-in USB interface (PIC18F2455) was included in the design for automated control of the programming tasks. Software will have to be written for a user interface, and the PIC will need to be programmed.


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Figure 5. Schematic for the clock synthesizer.

The selected divider is a Hittite? HMC361. That Hittite divider will run up to 10GHz and has a phase noise with virtually no degrading effect. However, the divider's output swing is only 0.8V_P-P or about 2dBm at 50Ω. The design goal is a 10dBm output (2V_P-P), so the Hittite outputs are insufficient and need to be boosted. There are other similar choices from On Semiconductor? and Zarlink?, but output swings were the same or worse and noise was not as clearly specified.

A simple transformer can be used to boost the amplitude on lower-speed clocks, but there are no commonly known > 2GHz transformers that run at a usable 4:1 ratio. Additionally, this approach creates awkward impedance for the design. Another solution is to use an active amplifier. There are a number of differential-to-differential amplifiers with > 10GHz of bandwidth, but some research is needed to ensure that the components meet the design's noise requirements. Whether the amplifier can be placed inside the PLL loop is also questionable, as the Fujitsu data sheet suggests a maximum prescaler input of 2dBm (1V_P-P).

Simulation Results

ADIsimPLL (written by Applied Radio Labs for Analog Devices) was used to analyze the proposed circuit. Models for numerous UMC VCOs are included. Figure 6 shows the phase-noise plots for a PLL using the UMC 4GHz VCO with no divider and the Crystek oscillator. Up to 2kHz, the reference oscillator dominates the phase noise. Beyond 2kHz, the detector phase noise takes over; at about 70kHz the VCO noise dominates.

Figure 6 includes the target noise mask from Figure 2 (thick black line). Obviously, the overall noise exceeds the mask up to 50kHz, resulting in a jitter of about 200fs. One issue with this particular simulator is how detector phase noise is treated. It should equal the specified noise floor of the chip (-219dBc/Hz) gained up by the VCO/PFD frequency, which should be 4000MHz/ 25MHz for this simulation, or 44dB. But the shift is 118dB. This too will need more investigation. But even when the PFD (phase frequency detector) noise is removed from the jitter, the result is still an abysmal 167fs.


Figure 6. Simulation test results using a VC phase noise was at 4GHz.

With the PFD noise removed, the filter is set close to optimal for the VCO noise peak at 10kHz. The major remaining problem is reference noise, and unfortunately, the better-than-mask performance beyond 40kHz is not enough to offset this noise. So the possibility remains that another oscillator, perhaps an OCXO, must be used to meet the phase-noise requirements.

The printed circuit board (PCB) for this design will include pads for three or four different XO footprints. Figure 7 shows the simulation results using the Vectron OCXO. Even with the PFD noise included, the resulting jitter is about 86.5fs. This jitter value offers some headroom both for the yet unaccounted for divider phase noise (which should have almost no impact) and for the amplifier stage that is probably needed.


Figure 7. Simulation results with the Vectron OXCO; phase noise was at 4GHz.