FPGA verilog实现的1602时钟计数器

原文链接：熬夜到了1点了，终于写出了1602的时钟计数器代码。为什么是时钟计数器呢？因为我还没来得及做校准时间，所以只能称之为时钟计数器，不能成为电子钟。网上很少用人公开这一类代码，一搜FPGA  1602，都是写一个静态的显示，在实际应用中，是没有用的，因此这个简单的例子，给大家抛砖引玉了！上代码： Qii 9.0编译过，21EDA 开发板测试OKmodule LCD  (  rst,  key1,  clk,  rw,  rs,  en,  data ); input clk,rst,key1; output rs,en,rw; output [7:0] data;  reg rs,en_sel; reg [7:0] data; reg [7:0] shi,fen,miao; reg [31:0]count,count1;  //LCD CLK 分频计数器 reg lcd_clk; reg [7:0] one_1,one_2,one_3,one_4,one_5,one_6,one_7,one_8,one_9,one_10,one_11,one_12,one_13,one_14,one_15,one_16; reg [7:0] two_1,two_2,two_3,two_4,two_5,two_6,two_7,two_8,two_9,two_10,two_11,two_12,two_13,two_14,two_15,two_16; reg [7:0] next,xianshi,two; parameter state0  =8&#39;h00,     //设置8位格式,2行,5*7    8&#39;h38;     state1  =8&#39;h01,  //整体显示,关光标,不闪烁  8&#39;h0C    闪烁 8&#39;h0e    state2  =8&#39;h02,  //设定输入方式,增量不移位 8&#39;h06    state3  =8&#39;h03,  //清除显示     8&#39;h01    state4  =8&#39;h04,  //显示第一行的指令  80H    state5  =8&#39;h05,  //显示第二行的指令  80H+40H        scan =8&#39;h06,      nul  =8&#39;h07;   parameter data0  =8&#39;h10,   //2行，共32个数据    data1  =8&#39;h11,    data2  =8&#39;h12,    data3  =8&#39;h13,    data4  =8&#39;h14,    data5  =8&#39;h15,    data6  =8&#39;h16,    data7  =8&#39;h17,    data8  =8&#39;h18,    data9  =8&#39;h19,    data10  =8&#39;h20,    data11  =8&#39;h21,    data12  =8&#39;h22,    data13  =8&#39;h23,    data14  =8&#39;h24,    data15  =8&#39;h25,    data16  =8&#39;h26,    data17 =8&#39;h27,    data18 =8&#39;h28,    data19 =8&#39;h29,    data20 =8&#39;h30,    data21  =8&#39;h31,    data22  =8&#39;h32,    data23  =8&#39;h33,    data24  =8&#39;h34,    data25  =8&#39;h35,    data26  =8&#39;h36,    data27  =8&#39;h37,    data28  =8&#39;h38,    data29  =8&#39;h39,    data30  =8&#39;h40,    data31  =8&#39;h41; iniTIal           //初始值 begin   //第一行显示 TEL:13868160569   one_1<="T"; one_2<="E"; one_3<="L"; one_4<=":"; one_5<="1"; one_6<="3"; one_7<="8"; one_8<="6";    one_9<="8";one_10<="1";one_11<="6";one_12<="0";one_13<="5";one_14<="6";one_15<="9";one_16<=" ";   //第二行显示 Clock：00-00-00   two_1<="C"; two_2<="l"; two_3<="o"; two_4<="c"; two_5<="k"; two_6<=":"; two_7<=" "; two_8<=" ";    two_9<="-";two_10<=" ";two_11<=" ";two_12<="-";two_13<=" ";two_14<=" ";two_15<=" ";two_16<=" ";       shi<=0;fen<=0;miao<=0; end     always @(posedge clk )   //获得LCD时钟 begin  count<=count+1;  if(count==250000)  begin   count<=0;   lcd_clk<=~lcd_clk;  end end always @(posedge clk or negedge rst )   //时钟计数器 begin  if(!rst)  begin   shi<=0;fen<=0;miao<=0;   count1<=0;  end  else  begin   en_sel<=1;      two_7<= (shi/10)+8&#39;b00110000;   two_8<= (shi%10)+8&#39;b00110000;   two_10<=(fen/10)+8&#39;b00110000;   two_11<=(fen%10)+8&#39;b00110000;   two_13<=(miao/10)+8&#39;b00110000;   two_14<=(miao%10)+8&#39;b00110000;      count1<=count1+1&#39;b1;   if(count1==49999999)    // 时钟计数   begin    count1<=0;    miao<=miao+1;    if(miao==59)    begin     miao<=0;     fen<=fen+1;     if(fen==59)     begin      fen<=0;      shi<=shi+1;      if(shi==23)      begin       shi<=0;      end     end    end   end  end    end  always @(posedge lcd_clk  ) begin   case(next)    state0 :     begin rs<=0; data<=8&#39;h38; next<=state1; end       //配置液晶    state1 :     begin rs<=0; data<=8&#39;h0e; next<=state2; end    state