一个已经layout完成的板子，重新导入网表报错，求大侠指点。

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'E:/work/PC5000214AV1.0/ELM/allegro';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/work/PC5000214AV1.0/pcb/PC5000214AV1.0.brd';
NEW_BOARD_NAME 'E:/work/PC5000214AV1.0/pcb/PC5000214AV1.0.brd';
CmdLine: netrev -$ -i E:/work/PC5000214AV1.0/ELM/allegro -y 1 -z E:/work/PC5000214AV1.0/pcb/#Taaaaaa02404.tmp
------ Preparing to read pst files ------
Starting to read E:/work/PC5000214AV1.0/ELM/allegro/pstchip.dat
   Finished reading E:/work/PC5000214AV1.0/ELM/allegro/pstchip.dat (00:00:00.05)
Starting to read E:/work/PC5000214AV1.0/ELM/allegro/pstxprt.dat
   Finished reading E:/work/PC5000214AV1.0/ELM/allegro/pstxprt.dat (00:00:00.00)
Starting to read E:/work/PC5000214AV1.0/ELM/allegro/pstxnet.dat
   Finished reading E:/work/PC5000214AV1.0/ELM/allegro/pstxnet.dat (00:00:00.00)
------ Oversights/Warnings/Errors ------

------ Library Paths ------
MODULEPATH =  .
           d:/Cadence/SPB_16.3/share/local/pcb/modules
PSMPATH =  E:\Library_spx\Symebols\
PADPATH =  E:\Library_spx\PAD\

#1   Run stopped because errors were detected
netrev run on Oct 31 10:07:33 2014
   DESIGN NAME : 'ELM0000203V1'
   PACKAGING ON Nov 17 2009 03:09:43
   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON
  1 errors detected
No oversight detected
No warning detected

没人遇到过这样的错误吗?

你是不是准备修改封装 。那就要把那个封装先删除掉，不然导不进去（这是画完的），可能原因就是这样我也遇到过。

不是修改封装，是原来板子上有几个器件是板子画好后手动放上去的，位号丝印是R*，我想重新导网表更新，总是导不进去。哪位高人有没有方法可以直接将R*修改为R23之类的