FPGA创建网表出错
时间：10-02
整理：3721RD
点击：
Scanning netlist files ...
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstchip.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstchip.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxprt.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat
ERROR(SPCODD-409):
Reference Designator: U1. Error at line 1386 in file F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat. Could not create new pin inst: GND# A1 .
Schematic Instance: @fpga_adc_usb.schematic1(sch_1):ins6253980@fpga_adc_us
b.\ep2c8f256_8g.normal\(chips) (MODULE: FPGA_ADC_USB; PART: EP2C8F256_5). Check the symbol for consistency of pin definition.
ERROR(SPCODD-383): Error at line 1386 in file F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat. Error loading the net list file
#86 Error [ALG0036] Unable to read logical netlist data.
Exiting... "F:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "f:\plasma_diagnosis\fpga_adc_usb_byzjj\fpga_adc_usb.dsn" -n "F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO" -c "F:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"
*** Done ***
从ALTERA官网下载的FPGA（CY2C8F256C6）的cadence模型，但是创建网表时就会提示上面的错误。改完一个就出现下一个。
求问有没有什么快速的方法，要不然一个一个改太麻烦了。
谢谢大家，急！
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstchip.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstchip.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxprt.dat
Loading... F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat
ERROR(SPCODD-409):
Reference Designator: U1. Error at line 1386 in file F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat. Could not create new pin inst: GND# A1 .
Schematic Instance: @fpga_adc_usb.schematic1(sch_1):ins6253980@fpga_adc_us
b.\ep2c8f256_8g.normal\(chips) (MODULE: FPGA_ADC_USB; PART: EP2C8F256_5). Check the symbol for consistency of pin definition.
ERROR(SPCODD-383): Error at line 1386 in file F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO/pstxnet.dat. Error loading the net list file
#86 Error [ALG0036] Unable to read logical netlist data.
Exiting... "F:\Cadence\SPB_16.3\tools\capture\pstswp.exe" -pst -d "f:\plasma_diagnosis\fpga_adc_usb_byzjj\fpga_adc_usb.dsn" -n "F:\PLASMA_DIAGNOSIS\FPGA_ADC_USB_BYZJJ\ALLEGRO" -c "F:\Cadence\SPB_16.3\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"
*** Done ***
从ALTERA官网下载的FPGA（CY2C8F256C6）的cadence模型，但是创建网表时就会提示上面的错误。改完一个就出现下一个。
求问有没有什么快速的方法，要不然一个一个改太麻烦了。
谢谢大家，急！
问题已解决：altera官网下载的模型，GND脚比如A1 A16等名字里有空格。
删除空格即可。