微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > PCB设计问答 > Cadence Allegro > 请高人指点,导网表错误

请高人指点,导网表错误

时间:10-02 整理:3721RD 点击:
#1   ERROR(310) Error detected saving layout file.
Cannot write drawing, 'D:/Dev/Hardware-DEV/02DESIGN/0202Project/V2_0/RNS510_Base_V2_0/RNS510_BASE_V3_0.brd' out to the file system: 'Database has a non-recoverable corruption, contact Cadence Customer Support.'.
#2   ERROR(102) Run stopped because errors were detected
netrev run on Jul 3 13:59:33 2012
   DESIGN NAME : 'RNS510_MOTHERBOARD_V3_0'
   PACKAGING ON May 28 2006 22:05:31
   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON
  2 errors detected
No oversight detected
No warning detected
cpu time      0:01:08
elapsed time柙
  0:00:01

NETIN时报如上错误,请高人指点

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top