Cadence 15.7导网表突然出错了~~

本来一直好好的，元器件都布局好了。然后去ORCAD里更改了一下原理图里几个电容的封装，再更新到PCB就出错了。有人有解决办法吗?不然白忙活了。
Allegro里的出错报告如下：
Cadence Design Systems, Inc. netrev 15.7 Wed May 12 21:32:04 2010
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH TRUE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'D:/CadenceWork/HongelDM642/PCB/allegro';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
NEW_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
CmdLine: netrev -$ -5 -i D:/CadenceWork/HongelDM642/PCB/allegro -x -y 1 -z D:/CadenceWork/HongelDM642/PCB/#Taaaaaa00436.tmp
------ Preparing to read pst files ------
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat
   Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat (00:00:00.04)
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat
   Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat (00:00:00.01)
Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat
   Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat (00:00:00.03)
------ Oversights/Warnings/Errors ------
#1   ERROR(102) Run stopped because errors were detected
netrev run on May 12 21:32:04 2010
   DESIGN NAME : 'DM642_PRJ'
   PACKAGING ON May 28 2006 22:05:31
   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON
  1 errors detected
No oversight detected
No warning detected
cpu time      0:02:36
elapsed time  0:00:01

哪位兄弟有用15.5版本的麻烦将 netin.exe和netrev.exe 这两个文件传一下给我吧。貌似是这个的BUG。谢谢

奇怪啊，allegro居然没告诉是什么错误，就说检查到了一个错误。