Negative Gain in odyseus's tutorial

I have read about Miller Capacitance topic in odyseus's website but i dont understand what -G (nagative gain) mean. 180 phase shift? How does this millter capacitance effect the input capacitance of a FET/transistor?
thank you

A good way of looking at miller capacitance is that at the Emitter of the transistor the capacitance is the capacitance of the base*(b+1)

It seems to me that they try to transfrom from capacitor from base to collector to a capacitor at the base to gnd and a capacitor at the collector to ground.