Gate level simulation

Every time when I do the gate level simulation, I get a lot of troubles such as the simulator is dead, the result is not waht I want, ..., I am wondering if my method has some problem.

Any good book about the flow chart to do Gate level simulation (including the EDA tools) for ASIC and FPGA?

Thaks a lot.

I think the simulator user guide is good tutorial, you can find the reason
from ncverilog or vcs tutorial. If your design is so big that the simulator
is dead, you can think about use Static timing Analysis and Formal Verification instead Gate Level simulation. It will save you a lot of time. :)
anyway, you post in wrong Forum. This is about RF & Microwave :?

Static timing Analysis is time consuming.

BTW, is Digital or RF IC design your project? If the former, STA is disburdened sometimes, though its power. When gate level simulation, pls pay more attention to RESET or SET signals.

Could you tell what trouble you have?