How dc voltage ripple influence the LNA performance ?

This will perturb the bias point and thus the device capacitances. This will produce phase modulation on the signal as well as IMD.

1.output will be modulate by DC ripple.
2.This also effect the bias point,so the output power is instability.

Too bad....

Voltage regulator of a LNA must be very "quiet"....

can all send any pappers

or ebooks

or web site

about the topic

tnks all

obviously every LNA designer may think that DC ripple may produce a modulation of the gain.
Surprendentely may personal experince on GaAs FET LNA showed the contrary.
Especially for Id and Vd parameter i've experienced a tipical sensitivity of less than 0.1 dB/mA (for a 10 dB Gain stage) and less than 0.1 dB/V (for 10 dB gain stage).
Higher sensitivity on Vg, but on Vg supply line, is more easy to cut away the ripple.

What cause the DC voltage to ripple?
Is there any design strategy or techniques to prevent DC voltage?

I'm also trying to design a LNA with embedded active inductor, hope I can prevent the DC ripple in my design as it degrade my LNA performance!

:D

Look at the protection diodes at the LNA input. If they have 200fF and the LNA 50 ohms you inject with -16dB noise at 2.5GHz from VDD. So not only bias is sensitive.

rfsystem...can you explain more about the 'protection diode'? Why you suddenly assume "So not only bias is sensitive"?

That means regular protection diodes for LNA input. In most cases there two. One to VSS, the other to VDD.

the protection diodes act as a "zener". They protect the FET from extravoltage