mc145151
http://www.freescale.com/files/rf_if...MC145151-2.pdf
does it has a charge pump inside it or not ?
what is the difference betwwen PDout and ΦR ΦV ..output from the phase detectors ?
the PDout produces correction pulses to the loop filter ? is it voltage or current pulses ?
It has two types of charge pump outputs. You chose which one of the two you want to use.
If you want a single ended output, like something to drive a passive R-C loop filter, use the PDout. In this case the VCO tuning voltage can sweep from perhaps 0.8 V to the powwer supply rail - 1V or so.
If you want to use an op amp with a dual power supply (+ and - voltages), then you use the Φr and Φv outputs into a differential amplifier. You would probably get better spur supression with this type of op amp, as you can exactly balance the two outputs to null when in phase lock.
for what application?
in each category different way to design LPF.
the application is FM transmitter ...
ok good now im interested in using the PDout to drive a simple RC passive filter....
if u looked in page 19 (datasheet) the PDout wave form has a constant voltage amplitude either VH or VL but the pulse width varies so how does it tune the VCO ?
Hi,
Look at this design :
h**p://es.geocities.com/la_fondadeariel/la_fondadeariel/txpll.htm
* = t
Happy new year,
Papyaki
Papyaki has good advice. At PDout, the series R41 and shunt C20 form a high frequency spike filter, and the IC6 is used as an integrator with R42 & C19 forming the lowpass pole frequency, and R43 & C19 forming the zero needed for stability.
If you do not use the op amp, you can just use a series resistor, like R41 only bigger in value, and a shunt capacitor like C20, HOWEVER you would have to add a resistor in series with C20 to ground to form a zero to keep the loop stable.
The best way to calculate these values is to go to the National web site and use their excellent PLL calculator program.
Hi,
Here are other good examples, have a look :
h**p://www.elektronik-kompendium.de/public/schaerer/pllsynth.htm
h**p://web.tiscali.it/ik8uif/24pll.htm
* = t
Regards,
Papyaki
There is a basic question that should be answered before choose if a loop filter will be active or passive, namely: Is the synthesizer wide or narrow band?
If the synthesizer is to be narrow band a passive filter should be chosen once this is the configuration that leads us to an ultimate noise behavior. In this case the loop will be free of the op-amp's noise.
If the synthesizer is wideband an active balanced loop filter should be used. This is because in this case the main source of noise will not be the op-amp's or the large series resistor that normally appears in series with the op-amp's input. The main source of noise will be the induced noise over the varicap circuit and to keep the varicap free of induced noise will be the true struggling in order to keep a clean synthesized waveform.
Just as a matter of figures, I have been designing several FM modulators in the range of 450MHz with 25% of tuning range rating a residual FM noise better than -65dB relative to a 25KHz peak deviation using active loop filters made up a low noise, low offset voltage op-amps connected to Fv and Fr phase detectors outputs.
NandoPG
good ...
but i want to understand more about the output coming from PDout .... as somebody said the chip has a chagre pump inside it ! so the PDout is current pulses ?
how this pulsessupposed to tune the VCO ?
the loop filter converts it to tunning voltage ?
i need more information......!
PDout is a tristate output, like a digital tristate gate. When there is no correction to be made, the output hovers at mid voltage.
For example, let say that you have a 5 volt power supply. When no correction is made, the PDout is held loosly at 2.5 volts.
If a phase correction needs to be made, the phase detector will connect the PDout pin either up to +5 volts, or down to 0V. It does this momentarily, once each clock cycle of the reference frequency at the phase detector. If the phase is way off, the momentary move up or down remains connected for a large % of the reference period. If the phase is almost there, the momentary move up or down remains connected for a small % of the reference period.
The PDout gate has current limiting in it, so the maximum current out is limited to +/-1 ma, +/- 0.1 ma, etc, depending on the chips design or how you hook it up/program it.
Somewhere in you loop filter there is a big capacitor that charges up or down depending on if + or - force is applied by the PDout.
good butt...
1- if there is no correction to be made .. PDout is high impedance state ok ? so how does it tune the VCO ?
in ur example u says it will hover around 2.5 voltages?
so this 2.5 voltage produces the frequency i want ? sorry i misunderstand it....1!
2- see this waveform
if there is an error (lagging or leading) the PDout is either Vh or Vl...but its pulse width refers to the time difference between the 2 phases to lock..? so how does this width converted to the correction voltage to VCO ? through a capacitor in the loop filteR?
that means the output is current converted to cvoltage by the loopfilter to tune the VCO? right ?
Yep, weird things happen when the VCO is locked up. The capacitor, due to internal leakage, leakage in the VCO, and leakage in the charge pump, will discharge from the desired voltage. Don't know exactly how this motorola PLL works, but even in a tristate condition, there will be leakage.
So the PDout pumps the capacitor to the voltage needed to maintain phase lock and steady state conditions, and over the following clock cycle the capacitor charges up or down due to these leakages. Then the PDout puts out another small pulse to inject just enough charge into the capacitor to keep it charged to the correct voltage. This goes on forever.
You may or may not actually be able to see this happen, since some VCO's themselves jump around so much in frequency vs time that the PDout is correcting for also. You may see huge PDout + and - pulses to combat the VCO phase noise, and not notice the constant bias of pulses to combat leakage currents.