Discussion on ASITIC and On-chip Transformer Design

Hi,

1. I'm now using the ASITIC to design a transformer, however, I found it's difficult to dump the transformer's S-Paramter (two port s parameter, the target transformer structure is just like the one indicated in the attached pix).

2. how to add ground to some of the inductor's terminals in ASITIC, as those shown in the attached pix: xfmr.jpg?

3. While designing a 1:1 transformer (1:1 here represents vout/vin=1:1), the secondary inductance Ls must be larger than 1/k2 (k is the coupling coefficient) times of the primary inductance Lp, based on the ideal transformer equations: vin=Lp(di/dt), vout=M(di/dt)=k√(Lp*Ls)(di/dt). Therefore, assuming k=0.8, then for the 1:1 transformer, Ls≥1.56Lp; for 2:1 transformer, Ls≥6.25Lp! if Lp=3nH, Ls must be larger than 18nH! Am I right here? I'm wondering if there's any published works realizing the transformers which output/input voltage ratio larger than 2:1, I mean vout≥2vin?


Thank you.

Ruri

You do an serious error. Primary and secondary inductances are not calculated as you mentioned.
The inductance values are depending on frequency of interest. At least minimum values of inductances
will define minimum frequency that you may use for the transformer.
For more information look at equivalent circuit of a transformer.

Hi, BigBoss,

Thanks for your reply.

Yes, I do know that: "The inductance values are depending on frequency of interest". However, I'm here talking about the vout/vin of the transformer under some specific frequency ranges.

Ruri

Well, I just wonder whether the 2:1 tramsformer can be replaced by a 1:2 one. The transformer with the ratio of 1:2 can provide the same Lp and Ls when the k is 0.7.

To my best knowledge Asitic can only output the s-p of an individual inductor of the transformer while another one is supposed to be gounded. It may not export the s-p as the schem u provided