Question about PA
We can observe that a PA will close to satuation region when we
apply maximum power level such as GSM PCL 5.
My question is, this phenomenon is for cost issue ?
Can we solve this by adding additional stage of transistor ?
Thanks.
The main reason to push a GSM PA in saturation (at full power) is to get the maximum Power Added Efficiency. If you check the plot PAE vs Pout you will see that the peak efficiency is at saturated power.
This is the beauty of GMSK (constant-envelope modulation) that is allowing doing this. Other systems, as EDGE or CDMA require linear amplification, working below saturated point of the PA.
Thanks.Vfone.
Add one more transistor in the IC (ex: 3 stage turn into 4 stage)
is useless for getting higher output power ?
My previous thought was adding one more transistor when you design
PA (4 stage PA) and it can get higher output power but cost more
than before(3 stage PA).I don't know this thought is correct or wrong.
Thanks.
Adding another front stage will increase only the overall gain. The saturated output power will be almost the same. For a GSM PA (3 stage design) is not a problem to get the overall gain. Usually first stage is in class A (high gain) and second and third stages in class AB. The distributed gain is somewhere 15+10+10. The high input power (what is normal for a GSM PA) helps lowering the overall gain.
It seems only two ways to get higher power without so reach saturation region.
(1) Increase DC voltage
(2) Increase input power
Is it right ?
Thanks.
Only increasing DC voltage will increase the saturated power. Input power will not increase this, because the PA is already in saturation at minimum specified input power and maximum PCL.
A GSM PA usually enter in saturation 5 or 6 dB below max output power.
Hi Vfone.
So when design PA, DC voltage & current have decided maximum power.
Even adding one transistor in the first or in the last stage is useless.
Can I say that?
Thanks.
The power of the last stage and the overall gain will dictate the output power.
If you add a stage in the front of the PA (last stage unchanged) the output power will be almost the same (last stage cannot deliver more power that was designed - only the overall gain will be higher).
Adding a higher power stage after the last desired stage, will increase the output power and overall gain.
In a multi-stage PA design, must be very careful making the power distribution on each stage.
Triquint is making a 4 stage GSM PA:
http://www.triquint.com/company/divi.../TQM7M4012.pdf
http://www.triquint.com/company/divi...20Note_1_3.pdf
As you mentioned the 3 stage PA is working as Class A - Class AB - Class AB.
What's about the 4 stage PA ?
And what's the advantage of 4 stage PA compare with 3 stage PA ?
Thanks for your advice.
In a 4 stage PA 1st stage is in A class, and the others in AB. The idea is to keep the first stage linear as possible, to don’t change the input impedance with input power. In GSM theoretically you don’t have this problem because the input power is constant, but is good to keep this approach (it helps for transient spectrum).
What is the advantage of 4 stages PA compared with 3 stages PA? This is a good question. I don’t see any advantage. Everything what you can get with 4 stages you can get with 3 stages with less headache. This is the reason that mostly of the GSM PA’s on the market, are 3 stages.
OK, 4 stage allow less input power (to get full power at minimum Vbat), but I think this is not a big advantage. Also the isolation is a little better (~5dB more compared to 3 stages).
The RX Noise Power is higher in a 4 stage PA.
the PA is 3 stage or 4 stage is decided by yhe system quest, if the PA gain is high,then y should use the more stage to arrive the aim! if the input power is lower,then y should use more stage!
other way,the device y choose is key,if every stage is high gain,y can use a few stage to arrive the aim!
the higher gain, the worse noise!
be careful
the worse spurs and more probability of self-oscillation.
I saw a power control document whose said
"With supply voltage control, the collector or drain voltage of the last one
or two amplifier stages are controlled. This limits the voltage swign of the RF
power transistors, hence reducing the RF output power, as long as the amplifier
is driven into saturation."
I don't understand the last sentence meaning
"as lon as the amplifier is driven into saturation" ?
In power control PA, it has saturated for all power level?
Hi ,Vfone . What maybe cause the PA into the saturation ,and what way to fix that issue matching or other way ? If the PA is in saturation ,what performance maybe fail ?
Best regards !
In a Collector Control design the PA could be in saturation at low levels (actually very close to saturation). This is the reason that the curve Pout vs Vapc looks different for a PA that has collector control, or one that has bias control.
For a GSM/GMSK PA doesn’t matter too much, because the transient spectrum spec at low powers is relaxed.
But at full power the saturation could make to fail transient spectrum (spectrum due to switching), especially at low temperature.
The saturation should be well controlled and never shall go in hard saturation (in hard saturation even the efficiency is going down). To avoid this, the output stage should enter in compression a couple of dB’s before the driver stage.
hi,ajhsu
l check your circuit,i appera in many document about the PA design!
this circuit imply that y can control the DC supply to control the maxim output power! In rf amplifier design, y shall notice a phenomenon,that is when y decrease the Vds,then the IMD and the maxim output shall decrease! this circuit imply that y can control the DC supply according to your input power , if the input power is lower,then y can decrease the supply,because y doont need high voltage and high current to supply the lower rf power swing!when your output power (also the input power is high)is high,then y can increase your DC supply!
an other way is to use the dynamic bias control is the same effect as the Vds control!
Can we measure the impedance of the PA output when PA is on work ?If we want to match the PA output to the load of the PA (including the ASM and antenna ), I think the impedance of the PA output is very important .
Everything counts on what PA sees for load. Because of High power output of PA, rarely people use network analyzer to measure S11 seen into PA output pin. However, PA house would make a load pull data for specified VSWR using load tuner for system engineer usage.
Hi Vfone.
As you said the 3 stage PA design usually set its power class as
ClassA-ClassAB-ClassAB.
Do you mean that each power level we controll collect voltage to set
each stage of transistor into nearly saturation region ?
Even output power is 10dBm but they're still working in nearly saturation
region due to we've set its collect voltage?
Thanks.