Phase Noise of A Closed Loop System (PLL)

Hi to all,
I would like to ask how to calculate the phase noise at the output of a closed loop system such as a PLL.

I have seen the method described in http://www.designers-guide.org/ by Ken Kundert. He incorporates the jitter in the behavioural model of the subsystems of the PLL and performs a transient analysis and finds the jitter at the output. After an FFT transform he gets the phase noise.

Using PSS analysis in Cadence I couldn't succeed because of stability reasons, the PLL would never lock.

In ADS, though it has some examples I couldn't customise them in my design and the analysis failed for stabillity reasons too.

I would like to share your opinions on this subject. Has anyone seen an accurate and relatively quick way to calculate the phase noise?
Thank you !

Hi;
Have you seen following books?
- Microwave and Wireless Synthesizers, Rohde,
- Frequency Synthesizers, Theory and Design, Manassewisch
- Frequency Synthesizer Design Handbook, Crawford

I also want the book
Frequency Synthesizer Design Handbook, Crawford
can anyone upload it?