What's the reason for performing power control loop for GSM?

Can someone please explain me what the main way of performing power control loop for GSM? What are their advantages and their drawbacks?
Some related articles or other stuffs? thanks to all.

RFCMOS

http://www.ensc.sfu.ca/~ljilja/cnl/pdf/ciampi.pdf
http://www.analogzone.com/hft_1206.pdf
http://www.xindium.com/pdf/HighFrequency_June2005.pdf
http://www.commsdesign.com/design_co...cleID=16506195

Thanks Vfone for your answer (always relevant!).
I'm more interested on integrated detector to sense the output power.
Is there any articles, thesis on this topic. how are they made in integrated GSM PAs?
Thanks in advance.

Usually manufacturers avoid a full integration of a closed-loop approach for GSM (PA, coupler and log-detector). They would prefer an open-loop, which is much easier to integrate.
Myself I was always for this idea that can get all the benefits of the closed-loop approach. Even the insertion loss of the coupler can be negligible if the coupling is >30dB.

SKY74073 from Skyworks integrates a closed-loop for GSM TX:
http://www.skyworksinc.com/products_...m.asp?did=3941

To sense the RF output power in a GSM PA definitely you need a coupler. I?ve seen some ideas that use just a small capacitor to sense the RF power, but the behavior under high VSWR was very bad.

For log-detector design you can search the net, which is full of ideas.
http://www.mwjournal.com/getblob.asp...=0404mwj20.pdf