low supply voltage, high output swing?

In 130nm cmos process, the supply voltage will be as low as 1.0v ± 10%. So, the worst case supply will be 900mV.

chip's output is differential, CML style signal and AC coupling is used. CML output driver is required to have swing as high as 900mVp-p.

Is that possible to be implemented without additional high supply voltage?

I do not think it is possible, since the output common mode will be as low as "900mV-450mV=450mV". And, when output reach max swing, the low output node will be as low as "225mV". That is too low. Tail device might fall out saturation, or output impedance will be distorted.

What's the real story behind those serdes products?

If each branch is biased 550mV, differential output will reach 1V max( Vcc voltage acc.to your assumption) and will drop 100mV min.So, differential output swing will be in that case 900mVpp..

Isn't it ?

If Vcc is equal to 0.9V, it's quite weird because of V(sat) voltage.This chip may use double voltage source such like +-1V ..

Namely 100mV is too low even for NMOS current tail source ( I assume a NMOS is used for tail current source ) In that case NMOS will work in Triode region which is unwanted...

I guess there is some lack of information about specifications.

i think it is pci-e spec