Challenge of RFIC Front-End design in Ultra-Deep Submicron?

When the technology goes into ultra deep submicron such as 0.13um, 0.09um,
What's the major challenge of CMOS RFIC design in this era?

We know the advantage of scaling is higher cut off frequency which means
lower minimum NF of LNA inherently. But what's the other issue?

the gate current , as the technology scale down the tunneling current in the gate incresae
also when u scale down the gain avilable from the device decresae , and all the short channel effects will be taken into account

khouly