LC-tank design in VCO

Hello to all
I'm doing simulation of a CMOS VCO using the TSMC 0.25um process.

But I don't know how to design a LC-tank in the VCO properly.
What is the optimum combination of the inductance and capacitance?

For example, for the 900MHz VCO, a LC-tank of 30pF capacitor and 2nH inductor in VCO is spoiled oscillation.
But the combination of 6pF and 10nH is induced a successful oscillation.

need help please If anyone has advice for me?

don't forget to take into account the Q factor for the L , and C , to get the series resistance of the resonator

also u should take into account the parasitic capacitances of ur coupled pair , and also u should design ur cross coupled pair well , so that it give a good startup factor

khouly