How the control voltage can influence the delay in VCDL?

(Referring to the PDF attachment)
In the symmetric load of the VCDL, a diode connected PMOS and a PMOS of same size are connected in parallel. The gate of the other PMOS is connected to the control voltage.
It is said that the by varying the control voltage the resistance of the symmetric load is varied and the delay of the cell is controlled.

1/gm resistance is parallel to the PMOS transistor. So the effective load resistance cannot be more than 1/gm.

So how the control voltage can influence the delay?

Thanks.