opposite result
I assembled it & while testing on VNA8712C i got exactly opposite result regarding return loss result.
In the simulator if the coupling capacitor value between the two stage is reduced,then the return loss improves.
But while testing on VNA exectly the opposite happens, i.e. while reducing the capacitor value, the return loss value is also reduced.
waiting for suggestions.
Have you been taking parasitics into account designing your PCB? These consists of stray capacitances of component pads to ground as well as inductance of interconnection pads. 1 mm length is about 1 nH inductance.
WinRAR your schematic diagram and layout plot and post here so we can take a look.
respected VSWR,
Here r all the files.
This includes simulation sch, real sch, pcb layout of pagemaker 7 in pdf, & s parameter files.
The linear design with s2p files for Q1/Q2 is using a bias of VCE = 4.78 V, IC = 9.81 mA for Q1 and VCE = 10 V(?), IC = 16.5 mA for Q2. But the bias in the real circuit seems to give approx. VCE = 3.5 V, IC = 11.5 mA for Q1 and VCE = 4.3 V, IC = 21 mA for Q2. This should be easy verified using a voltmeter. Incorrect bias gives different S-parameters.
L4 is 3 mH. This is too high as SRF is about 1-3 MHz for this inductor value. This means L4 is strongly capacitive att 100 MHz. Maybe 10 pF or so. Use 1-3 uH for L4 instead.
I will recheck the value of L4 once more.
How u got the value of biasing voltages?
Is it possible to see this in serenade 8.7 or genesys 7.5.
I can use this software if required.
Check the stability of the amplifier.It might oscillate..