The first step for designing a PLL

hi!i am a freshman in designing pll.i want to know the first step of designing a pll.how the behavior model be built?today, i tried to build a model of pll just using cells offered by virtuso .for example,i used the vco in functional lab,filter in the rfLib and so on.i want to replace these cells using the real cells later.how about this process,what is the correct process?give me some help and advice!
thanks!

Do you know the performance of the pll that you are trying to achieve? That generally a good starting point. A pll is a closed loop control system, and it's unlikely that one you simply throw together will work.

Dave

u need first to know how to model the PLL and then begin the simulation
also a very good tool for PLL design is systemvue

khouly

thanks a lot!
I am reading the book written by Best,i know the basic concepts about pll.i also kown the specifications.then what is the next step?how about just using spectre to build a model using ideal cells and set the parameters? if the specifications are met,i will turn to the design of the basic cells,and i will replace the ideal cells with the realistic cells to see whether the specifications are met.how about this process?
give me some help!
thanks again!

i didn't use spectre but i used matlab to simulate the PLL in both S and time domain

khouly

if i use spectre to build the behavioral model,should i build the model of the basic cells such as vco using verilog_a?it is more convenient to simulate the pll in the transistors level using spectre than matlab.right?

for system level with high level of abstraction u can use both MATLAB and verilog_A
but in transistor level u can use only spectre coz matlab doesn't support transistor level simulation

check this http://www.designers-guide.org/Analysis/
there are many tutorials how to simulate the PLL phase noise with verilog A

khouly

i am starting anew pll design too and here is my suggested strategy:

1. start building models for pll in AC domain.
2. design the pll parameters and verify them in your ac model.
3. build a transient time model for each block using the parameters (it's recommended to use verilog A in transient time models) u have verified in ac domain.
4. make sure the performance is as expected.
5. start building each block in transistor level and replace the verilog a model of the block by the transistor level model and make sure the performance is not affected. (you can even use mixed type of models i mean some blocks are in transistor level and other are in verilog A)
6. Congratulations u have finished the design.

thanks a lot!
what is the difference between ac and transient model? is ac model linear while transient model is nolinear?does ac model refer to the the lock state? does transient model include unlocked state?and what is the difference between Verilog-A and VerilogAMS?