switching mode PA driver
时间：04-09
整理：3721RD
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Hello All,
I am designing a 10dBm FSK, 900MHz switching mode PA in CMOS. I cannot find good information on optimizing the driver stage. So I need some pointers here.
My approach is to use a chain of inverters, with their size increasing from the divider to the output stage. Given the load cap of the output stage, what is the best way to optimize the driver? For example, how can I determine the best number of stages and their scaling ratio?
Should I follow the same approach as in digital drivers? or is there a better way since perhaps the requirements are different?
Thank you in advance ...
I am designing a 10dBm FSK, 900MHz switching mode PA in CMOS. I cannot find good information on optimizing the driver stage. So I need some pointers here.
My approach is to use a chain of inverters, with their size increasing from the divider to the output stage. Given the load cap of the output stage, what is the best way to optimize the driver? For example, how can I determine the best number of stages and their scaling ratio?
Should I follow the same approach as in digital drivers? or is there a better way since perhaps the requirements are different?
Thank you in advance ...