Issues with Agilent E-phemt PA design
时间:04-09
整理:3721RD
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Hi All
I am trying to design a PA using Agilent (Avago) ATF-50189
I downloaded the data sheet and the model files, including also a design example from an appplication note.
I am ulsing the load line methode of Cripps to design the PA
in the data sheets there is a table called absolute maximum ratings.
in it I found that VDS maximum is 7 v, and it is written Assumes DC quiescent conditions, does this mean that this 7 volts are only for DC but the peak AC voltage csan exceed 7 volts.
in the same table for VGS it has a range from 0.8 to -5 and also written Assumes DC quiescent conditions, although it is written that Pin maximum is 30 dBm
I simulated the supplied example and found that AC volatges at the gate and the drain exceeds these maximum ratings. also the drain voltage goes negative
according to my knowledge applying to much positive voltage to the gate will lead to current flowing in the gate metal semiconducto junction .
anyone has experince with these transistors or similar E-Phemts
Thanx in advance
I am trying to design a PA using Agilent (Avago) ATF-50189
I downloaded the data sheet and the model files, including also a design example from an appplication note.
I am ulsing the load line methode of Cripps to design the PA
in the data sheets there is a table called absolute maximum ratings.
in it I found that VDS maximum is 7 v, and it is written Assumes DC quiescent conditions, does this mean that this 7 volts are only for DC but the peak AC voltage csan exceed 7 volts.
in the same table for VGS it has a range from 0.8 to -5 and also written Assumes DC quiescent conditions, although it is written that Pin maximum is 30 dBm
I simulated the supplied example and found that AC volatges at the gate and the drain exceeds these maximum ratings. also the drain voltage goes negative
according to my knowledge applying to much positive voltage to the gate will lead to current flowing in the gate metal semiconducto junction .
anyone has experince with these transistors or similar E-Phemts
Thanx in advance
according to the datasheet ,
the VDS is set to 4.5 or 3.5 V , which is near the half of 7 V , which mean , when u make a PA , ur max swing is 2xVDS which is 7 , so u still in the safe region , coz the AC voltage will be instantionse ,
khouly
I am trying to use this transistor to design a Classn E amplifier this means the swing will be 3.2xVds
i don't have experince in class E design
we need a expert to answer ur question ?
but u can try to make use it , maybe the transitor will be damaged
khouly
