Envelope amplifier-HIGH EFFICIENCY PA-DC-DC converter

HI,

I am designing an envelope detector and a DC DC converter which provides continuous voltage according to the input RF signal envelope.

I encounter some difficulties with the switcher stage composed of NMOS transistor, It seems that the NMOS doesn't operate and I don't know why...
My supply voltage must be around 50V but I don't know if the NMOS available in the ADS "Devices-MOS" library are able to get high voltage level?

To be more precise I want to get an output voltage according to the envelope shape of the RF signal, that means when the envelope drops to zero, the Voltage output should decrease to zero at the same time.

I give my project in attached file.

Thank you very much for your attention

Can not read any of those files.

What is the intention, to dynamically detect modulation peaks and provide more amplifier headroom, or long-term see the input power and over seconds time period throttle down or up the amplifier potential output power?

I do not think a switching regulator will respond to a desired output voltage change in quicker than a millisecond or so.

These files are ADS files including networks and datadisplay files of the project.
Do you have eesoft ADS software?

THe goal is to get a dynamic supply voltage at the RFPA drain, the Vds voltage must follows the envelope of the RF input signal aids of the envelope detector+DC-DC converter.

The RFPA needs 50 V drain voltage assuming that I have a 50V DC source.

I join a figure to be more precise.

thank you

who can help me?

Do I have ADS? No, thank god!

Like I said earlier, how do you intend to have the dc-dc converter respond fast enough to the modulation envelope. Your dc-dc converter is probably 1000 times too-slow.

Thank you biff44 for your comment.

The modulation envelope used correspond to 10MHz, you think it's to high for DC-DC converter, I thought NMOS transistor were able to reach this frequency level.
I though that linear op amplifier associated to NMOS switch stage could provide dynamic voltage .


thannk you

jayce

Well, let me think this through.

You have modulation changing at a (chip) rate of 10 MHz. That means every 100 nS you change states. If you want no settling time errors in demodulating the data (like phase lag errors rotating the constellation), that means you probably want the "voltage regulator" portion to settle out in say 20% of the 100 nS, or 20 nS. To settle out in 20 nS, you would need a control loop bandwidth in the "voltage regulator" or perhaps 2.2 /20 nS = 110 MHz control loop bandwidth.

The typical control loop bandwidth for a switching regulator is on the order of 10 KHz, so you would have to worry about all sorts of parasitic reactances in the switching regulator, chief among them would be a inductor that can work up to 110 MHz. You would probably need the switching regulator to be switching at well over 110 MHz itself! Doesn't seem practical! The only way this might work is if the modulation changed in a step function only rarely, like you sense you are far away from a basestation, and decide to transmit at high power for the next minute. In that case you can just send some garbage header bits, detect the amplitude, and casually settle in. Then you could use a much smaller control loop bandwidth.

About the only way I could see it happening if you had an open loop system. Maybe have a wideband envelope detector driving a very high speed Analog-to-digital converter, which uses a very high speed prom look-up table, and then sets a fixed DC voltage on the RF amplifier through a high speed DAC. You would still have to worry about how to analog process the envelope detector output, lowpass filter, sample and hold? You run the risk of not responding fast enough to a sudden change in envelope, and therby corrupting the first few bits. Something like QAM modulation would be very unforgiving of losing a few bits every time the amplitude changed!

The good news is that you would not need many bits in the ADC and DACs--maybe 2 or 3 bits would be sufficient.