genesys amplifier design

some questions about genesys&co
i try to design a transistor amplifier with genesys
of the transistor i have different spice files (s-parameter for differnt biasing and one file with some transistor datas - parasitic model&other (Lb,Le...and IS,BF...))
i′m talking about bfr540.
first i′m designing the bias circuit.
if i add the input and output port after the bias design, the voltages change.
should i ignore that? or should i add ports before biasing? is it better to design impedance matching before biasing?
for matching i take s-parmater file and for biasing the other(with parasitic model) - is that the correct way?
is there any nice book about genesys or do you have some tips for me?
i′m sorry for my bad english =)

nice greetings
bob

Have you inserted DC blocking capacitors at ports ?

the voltage change only happened, if i add lumped elements to the match. (sorry was my mistake - if i add only the ports the voltage is ok). now i placed the dc blocking condensator closer to the transistor (they were placed after the lumped element) and the voltage is ok :)
old: trans....lumped element(s).....dc blocking...port
now: trans....dc blocking...lumped element(s)...port

thank you for your help

Hello:)

A new problem occurred:
i added a bend to the bias circuit. after this the bias voltages changed extremly. if i use a straight microstrip the voltages became ok. why this happens? (i need bends for a wavy line)

nice greetings