difference in phase noise of CMOS process and bipolar proces

To design phase noise < -150dBc, Can be designed in CMOS process or not?
In general, crystal OSC, what phase noise can be realized in CMOS process? and what phase noise can be realized in bipolar process?

Do you mean the nosie floor?
MOS can do.
If not, what is your spec?

CMOS will be 20-25 dB worse in phase noise than a bipolar process. Possibly even worse very close to the carrier, since CMOS typically has worse flicker noise.

Thanks,
The spec. : To design OCXO, phase noise requirement is 155dBc @ 1KHz. Can it be realized in CMOS process, if design with bipolar, is it easy to be realized or not?

Maybe bipolar process can do.
But what's your frequency?
If it is larger than 1GHz, I think it is impossible.