the gate line of CMOS power cell problem

Hi, Now I'm designneing the RF CMOS power cell, I want to design the proper gateline netwirk with EM simulator, but found that it is so sensitive to the conductive substrate? (I mean when the sub is setted with cnductive, the gain will degerate a lot but when it is setted with nonconductive, that gain looks like good), bdesides, I found that when i put metal (ex.M1) under the gateline, for some foundrym it will be good, but for some foundry, it doesn't, looks like so wired! whi can tell u something about it? who has some experience? Pls give me some helps! thank u!