Question about pll control voltage

时间：04-09 整理：3721RD 点击：

Hi,every one.

I have designed a cppll,the vco used in it is a LC VCO. But when the pll is locked.
The signal in LC VCO output node will coupled to the VCO control node through the varactor. This cause the control voltage not be stable in a value, but fluctuate around some value. The fluctuate value can achieve about 15mV.

So can some one tell me how to reduce the fluctuate value, and make the control voltage stable.?

What is the PLL that you use?
What order of system ? (more than 2nd order is "dangerous")

Altough PLL has nolinear behavior, classic control theory is used providing good results to insure stability.

May be you already read:

http://www.national.com/an/AN/AN-1001.pdf

https://www.edaboard.com/ftopic126150.html

And One of the classics: http://www.amazon.com/Phaselock-Tech.../dp/0471430633

Best Regards

The pll is a cppll .
I have simulated it in simulink and veriloga. And there is no stable problems.
The voltage fluctuate in locked station.
So I want to reduce the fluctuation under 1mv.

The control signal cannot be "stable" because it has to control - that means continuosly to correct deviations of the output signal. However, one should try to limit these fluctuations to a tolerable value by a careful design. If 15mvolts are to high you have to look into your design in order to find the reason. In this context: How can you know that "the signal in LC VCO output node will coupled to the VCO control node through the varactor" ?

Yes the signal cannot be "stable", so I want to reduce the fluctuation below 1mv.
There are two reason for the fluctuation in the control line I think:
first is the reason you have said:continuosly to correct deviations of the output signal.
second : because there are varators between VCO control line and VCO output,and the varators are not exact equal every instant time,so the in phase and out phase signal of the VCO output will coupled through the varactors to the VCO control line.
Because the second reason, the fluctuation in my cppll is to large.

[quote="LvW"]

15mV?
Do you use the second order loop filter?
If you use the 3rd order, the swing can be redcued.
But， it is detemined by the value of loop filter.
And, if you reduce your bandwidth of your pll, the swing can also be reduced.

Hi Kooller,

I think one of the most important information is still missing:
What is the FREQUENCY of the "fluctuating" signal in comparison to the VCO frequency ?

Hi Kooller,

that′s what I′ve thought !

Explanation: At the PD output there is not only the wanted signal (proportional to phase resp.frequency offset) but also a second term consisting of the SUM of both frequencies (and if in-lock it′s the double of the VCO).
This term is always present and you have to supress it with a low pass which has to be designed carefully not to decrease loop stability. That′s PLL theory.

there is no need to reduce or eliminate these oscillatiots
this the inherent quality of LC VCO based PLL

these will be at the double frequency of the VCO frequency.

these may be of magnitude even more than 30mv

There is no need ? I think, it depends on your quality requirements. These fluctuations (the term "oscillations" is not correct) cause VCO output jitter !

Hi LvW

Yes ,it can be supress by the LPF if we make the capacitor in it larger. When I make the capacitor 20 times larger than the value I first designed. The fluctuating voltage will be supressed to 3mV. But in that case, the capacitance will be as large as 4nF. and this is too large for integrated. I would like to design the synthesizer for fully design .

And my synthesizer is a integer one. The input frequency is 1MHz, output is 1.8G.
The bandwith of the loop is 50kHz. So I wonder how i can supress the fluctuating voltage in the control terminal of the LC VCO, and also the synthesizer is suitable for integrated.

Added after 17 minutes:

Why there is no need to eliminate the fluctuation?
I think the fluctuating voltage in the control line will bring large frequecy deviation and make the phase noise of the synthesizer worse.

Quote: Yes ,it can be supress by the LPF if we make the capacitor in it larger. When I make the capacitor 20 times larger than the value I first designed. The fluctuating voltage will be supressed to 3mV. But in that case, the capacitance will be as large as 4nF. and this is too large for integrated. I would like to design the synthesizer for fully design .

The normal way to solve this filtering problem is to use an additional lowpass specifically designed to suppress the double VCO frequency at the PD output. If properly designed this filter can be of 2nd order and has only minor influence on loop behaviour as its pole does not dominate the dynamic properties.

Why to use lowpass component at the PD output? Wasn't the lowpass filter followed the charge pump?

And the problem is the parameter of the LPF is always determined by the bandwith of the synthesizer. In the synthesizer i designed the bandwidth is 50kHz . but the bandwith of the LPF is outside the 2rd harmonic of the VCO output frequecy. To make the bandwith of the LPF smaller I have to make the capacitor of the LPF larger. I have tried that to supress the fluctuation of the control voltage with in 2mV, the capacitor should be as large as several nF , which is not suitable for integrated.

This sounds like a misunderstanding. When I say PD ouput I mean (in your case) CP output since I regard the CP as part of the PD.

Quote: And the problem is the parameter of the LPF is always determined by the bandwith of the synthesizer. In the synthesizer i designed the bandwidth is 50kHz . but the bandwith of the LPF is outside the 2rd harmonic of the VCO output frequecy.

The bandwidth of the lowpass is larger than 2*VCO frequency ?

Added after 22 minutes:

Only now i have realized that your PLL is a synthesizer with a frequency divider in the feedback loop. That means that the phase detector has to evaluate two incoming frequencies of about 1 MHz, correct ? In this case, the double frequency I was speaking of in my last reply is about 2 MHz. But you have mentioned that the unwanted "fluctuations" have a frequency of 2*VCO >>> 3.6 GHZ, correct ?
If this is the case, I don′t know the source of these disturbances.

Hi,
As far as I understand, due to the finite dead zone in PFD, there is a non zero DC value at Vcont.may be you can tweak around your PD or PFD a bit?