How to define the input power for LDMOS transistor?

I want to see the optimum load of LDMOS transistor with load pull. But how to define the input power? How much should I use for input power?

usually, optimum load impedance is defined at 1dB compression point, and then you have to put related input power.

you mean I need to tune the input power so as to get the 1dB compression point?
Optimum load impedance should be the compromise between power and efficiency. Normally, we don't choose impedance at 1dB compression point. Right?

Yes, you seep the input power to get the P1dB, but load impedance choice depends on the application you are focusing, if you want a tradeoff between output power and efficiency I advise you to plot the PAE & Pout contours of your device, that will help you to make a choice and get an idea .