lo buffer

Dear all,

I just design a simple LO buffer, which locates in between PLL output and mixer LO input. The buffer just a simple common source amplifier with current source tail and inductor loading.

Actually, do I need to simulate the stability of this buffer? it is 0.1Vpk-pk single ended input and 0.4Vpk-pk single ended output. Buffer does not feedback path. If it did not need to see the stability factor, WHY? If it needed to see it, what method did it see it? using sparameter or gain phase margin?

Thanks

wccheng

are you saying that you just designed an RF amplifier as part of a PLL, but you are not sure if it needs to be stable of not? Well......lets say it was sitting there oscillating strongly at 1 GHz, what might that do to your PLL locking operation?