perfomance degradation of LNA before and after layout

Hi, everybody,
Now, I am designing a LNA. Before layout, the gain is about 18 dB, quiescient current is 16.7 mA.
However, after the layout, the gain is 15 dB, and the quiescient current is about 14.5 mA. The gain loss is as high as 3 dB.
Even when I increase the VDD to a level which make the quiescient current is equal to 16.7 mA, the gain loss is still 2.5 dB.
Does anybody can tell me the reason of this too much gain degradation? What should i pay more attention to when design a layout of LNA ?
Thanks so much!

Check the power supply design. adjust the gate voltage to get exact VDS.

Before layout, the Vgs=663mV, Vds=452mV.
After layout, the Vgs=647mV, Vds=447mV.
Do you think this variation will lead to 3dB gain drop ?

Is Vgs > Vds?
I think it could be driving in to saturation?
What is the frequency of operation?
Is source pin of LNA grounded immediately or any feedback technique is used?
Will you share the design ?

Pre simulation results:Vgs=663mV, Vth=502mV, Vds=451mV, Vdsat=147mV.
post simulation results: Vgs=647mV, Vth=502mV, Vds=447mV, Vdsat=139mV.
The topology is a classical cascade inductive source degeneration. pls see in attached.
Thanks

At which frequency do you work on? It's quite important.
Why the model of the inductors does not cover the serial resistance ? Why so the model is primitive..
There should be serial resistance,parasitic capacitances to the sustrate and couplings between the inductors..etc.
If you use so simple models, of course you'll find a degradation between layout(extracted) and schematic..
Especially higher frequencies, this degradation will be obviously high..

In the schematic you will not find the inter connecting transmission lines.
The feedback inductor is 0.45*3 means it serving 0.15nH only.
But the inductance given by the line ( in the layout) from NM1 to inductor is causing this problem(I guess)