LO and QAM64

Hello all. I'm trying to make the receiver to convert QAM 64 from 6 Ghz to IF=0.8 Ghz. I have bad BER=5*10^-6 which constantly sweeps. I don't know what to do. When i apply IF signal to cable receiver and TV set i see the fade of picture sometimes. SNR is more than 35 dB. May be i should change my LO. LO consists of frequency Synthesizer ADF4156 with VCO HMC431lp4. What bandwidth of loop filter should i choose? 15kHz or 30 khz to improve Ber? I simulated my LO in ADIsimPLL from Analog device. Project is attached below.

Why do you directly suspect the LO/synthesizer? I would first investigate whether the intermodulation distortion of different subcarriers is not blocking you. TV amplifiers always need to be very linear with very large backoff.

Do you have a specsheet and architecture?

Yes, you are right. I see some subcarriers in out of band and OIP3 of the receiver is +20 dBm but the input signal is applyied to have less than 0 dBm at the output. As i told SNR is more than 30 dB.

I've just take a quick look at your project and made some modifications (I'm not really familiar with ADIsimPLL, but I've tried to do my best).
It seems to me that you have a large noise coming from VCO and so I have enlarged the bandwidth and phase margin.
The integrated phase noise now is lower (it was 1.3 deg in the original file now is 1.0 deg)
I have also removed the last pole that seems not useful to me.

Try this config and see if you SNR improves.

By the way, do you have a measurement of real phase noise with spurs? Maybe the real system is performing in a different way respect to simulations (sometimes it happens..)

What makes me worry is the sentence in report:
First Fractional-N Spur Location (estimate)
First fractional-N spur at: 105kHz
The software does not takes into account of spur degradation. If this is the root cause of bad performance, my suggestion will give you worst results (as I am enlarging the bandwidth, the spur will be higher).

I hope it can help.

Mazz

Mazz thank you a lot. I'll try it tommorow when i'm at work. But could you explan how you calculated integrated phase noise? pls

The software does it for you, look at report page.

Mazz

Oh, yes, it's in report :) I've just made your PPL in receiver. The view of phase noise is realy more better, but it has spurs at 20kHz of 40 dBc, at 35 kHz of 39 dBc, at 120 kHz, and many small spurs. I know you notified me before. I can get out of it reducing the bandwith of Loop filter. May be i should reduce the current of charge pump to 0.3mA and recalculate LF for 50kHz?

Spurs can be generated from different sources:
Reference, fractionality are the main one.

Being the 20 KHz the lowest one and INSIDE the BW (50 kHz) it is not filtered out by loop filter.

You have 2 options:

1. Understand where the spur come from and try to modify your circuit to avoid its generation (for example, if it comes from reference, change reference freq.)

2. reduce loop filter BW in order to filter it out.
But in this case you need to have a very small BW (< 1 KHz) that will increase a lot the settling time (but if this is not an isue for you, you can do it) and, in your case, increase the phase noise (as you will see you VCO noise once again).

So I suggest you the first way.
Do you already know where this spurs comes from?

Mazz

Hello Mazz. At first thanks for helping.

I watch the signal from reference. My reference is 27Mhz and spurs are at 54Mhz of 30 dBc (the second harmonic) and at 81 Mhz of 20 dBc (the third harmonic). May be i should design filter to reduce these harmonics. How do you think it will help?

Don't worry about the harmonics of your reference clock.
Your reference signal just has to be clean "inside" de BW for your PLL: Flo-BW to Flo+BW ( a little bit more of course because out of band spurious are attenuated in 20dB/dec then in 40dB etc... depends of number of poles) .

Problem: it isvery hard to check the purity of the referenceclock, as the PLL will "amplify" the reference with the ratio 20log(N)
In case you want a phase noise of -110dBc/Hz at 6GHz and you have a 100MHz reference, you should check that the ref noise is lower than -110-20log(6000/100)=-145dBc/Hz !

I have the impression you need to clarify first your LO specification.
Max RMS phase error
Max spurious level in dBc

Then you can select a VCO and a PLL circuit according to your needs.
Here you have a fractional architecture without sigma-delta. You can expect a quite high level of spurious at rather low frequency offsets.
If you work with this circuit you will need to find the optimum BW, but you can also try to avoid some fractional ratios (the ones generating low-frequency unfiltered tones).

Added after 1 hours 50 minutes:

>May be i should design filter to reduce these harmonics. How do you think it will help?

No the harmonics are welcomed here since the first block of the PLL is a divider. The phase is the only important thing. Ideally, the ref signal is a square wave (lot of H3, H5 ...).
If you enter a sine-wave as the reference signal, you are more sensitive to possible supply noise up-conversion.

agree with courcirc8.

I suggest to you the following test:

set a PLL freq that is an integer multiple of ref freq, for example 5562.000 MHz (27*206) and see it the low freq spurs are still there. With no fractional ratio, no fractional spur.

If spurs does not change, thay come from another issue.

Mazz