RF LNA chip test procedures?

Hi, I have a question about RF LNA chip test procedures.

The LNA have been soldered on the PCB, with RF in, out connected to SMA connectors, and DC pin to regular connector. It is self-biased MMIC LNA operating at 5.8GHz. In order to test its small signal gain and P1dB, what are the test procedures? Can somebody check the following procedures correct or not?

1. Adjust the network analyzer output power lower than a certain level (-10dBm in my case, which the LNA gain is 20dB, and P1dB is about 20dBm). Make the SOLT calibration for the network analyzer.

2. Hook up the test cables from network analyzer to the RF in and RF out of the LNA PCB RF connectors.

3. Turn on the DC power supple, set the voltage to be 0V.

4. Hook up the test leads from the DC power supply to the LNA PCB DC connectors.

5. Increase the DC voltage to the optimal voltage of the LNA.

6. Read the S-parameters from the network analyzer, record the small signal response.

7. Increase the network analyzer RF power output, until the gain (S21) drops 1dB, record it as P1dB.

Please advise me any issues about this procedures, thanks.

You should be far from Po1, at least 20 dB far, so set VNA power level to -30 dBm No! turn on PS and set the voltage to the nominal voltage, then switch it offNo! Instead, switch on the PS. A quick turn on is everytime accepted, while a voltage ramp isn't OKOK8. before spar measurement, You should check the followings:
Does DC current is nominal?
Does the LNA is self oscillating?
In order to check self oscillations, connect a SA at the out, then to the in, the to out but trough a directional coupler and leave both the ports to open and short.
Look for oscillations in the full avaliable spectrum ( i.e. KHz to 26 GHz)