Integer N PLL - lock times
Thank you in advance
Lock time is inverse proportional to PLL filter bandwidth.
You should 2 things simultaneously
-Locking time
-Bandwidth
Also, you have to find a optimum way between trade-off
Hi Bigboss,
Thank you for your input. With a channel spacing of 100kHz, Loop bandwidth say is 10kHz. This means that the settling time taking approx. 10/LB = almost 1ms. This is a little too much time for the application.
I am wondering if there are things that can be done to speed up the lock time - eg. perhaps use a mixed mode with also frac N mode of operation to get to the settling time quickly.
I also want to get a sense of what others have been able to do - on this board, someone posted saying they could get settling times to under 200us for 200kHz channel spacing. If there are any relevant references or other publications, I would like to get these.
Are you targetting to a FCC 15.247 frequency hopping application? Most systems in this field are using a fractional PLL as far
as I'm aware of. Although relative PLL lock time is in fact inverse proportional to PLL filter bandwidth, the absolute amount
depends on many other parameters, particularly the initial VCO control voltage after a frequency step. Another option to
achieve fast locking is to try an almost exact frequency preset based on stored values (determined by a system self calibration).
Also mixed operation modes can be a solution, but I think, then you can use a full featured fractional PLL as well.
Some PLL ICs have a pin to speed-up the charge time of PLL filter capacitors.This can help you..
Locking time is also depended on charge pump current.If you're able to increase the charge pump current,locking time will be faster.
Hi FvM,
It is for a 15.247 application and we also have very tight area and power consumption requirements (<1.2mA at 1.8V).
do you have any references/publications on the frequency preset technique?