layout problems in tsmc 65nm
1. when I used the self-generated layout for the transistor, I found different extraction results when the layout is put in different orientations, vertically or horizontally. This gives me a very different result when simulating the fmax. Has any one met the same problem? or can some one explain it?
2. I want to modify the layout of tsmc's rf transistor layout to optimize the fmax, but I wonder that kind of changes are allowed without changing the intrinsic transistor's behaviour and still having a proper simulation? And if I modified the layout, could is still be matched to the transistor in schematic and LVS clean?
I am starter, and I know I am using a very advanced technology, so hope some one could help me on this.
Thanks in advance.
In fact our group was doing design mainly using 90nm, 65nm and 45nm. I think your result is reasonable different direction having different fmax because of the mobility. If you want to change the layout, in fact currently we have tried to optimize the Smic 65nm transistor, and our layout having Fmax two times than the PDK gives. From my point of view, if you didn't having the measurement result, please don't try to do that.
Hi ppboyindream, thanks for your reply.
I also think it will be totally a risk to modify the layout without measurement and refining the transistor model. But my supervisor insisted that it will be no problem...
At the moment, what I did is to flatten the pcell of the transistor layout and modify on it. Then extract the rc parasitics within. The simulation could show an improvement upon the PDK layout. Although I doubt how much I could trust the result...
It would be nice to hear your advice on this.
Cheers,
jimiblues