cox cmos lna
I have designe a low noise amplifier, but I don't know if my procedure is correct, is there someone that can help me? in attached there is the circuit.
Thank you
what is your procedure? what is your problem
I can guess that my procedure is correct, but how can I test this LNA with cadence to verify if it is correct or not correct? The two PORT in the schematic how do i have to use? you can help me?
Add S2p analysis
define Port 1 is Input
Port 2 as output
simulate check S21, NF, S11 etc...
David
If you designed in Cadence, read Spectre documentation.
Hi,
what does mean "procedure"?
You mean circuit topology? simulate procedure in cadence? or circuit calculations?
To design the differntia LNA :
1) The firs step is to define the optimal width of the input trasconductor
Wopt=1/(3*ω*L*Cox*Rs)>>>>where ω=2*π*f
L=length of Mosfet commonly is the minimum length
Cox=oxid capacitance
Rs=input resistence
2)We have to copute the parastic capacotance of input mosfet (M1,M2)
Cgs=(2/3)*W*L*Cox+W*Cgd0
Cgd0 and Cox are dependent on tecnology
3) We can compute ωt=(gm/Cgs)
4)Ls=(Rs/ωt)
5)Zin=s*(Ls+Lg)+(1/s*Cgs)+ωt*Ls
In attached there is the schematic
If there is some problems you can ask me ; )
Dear,
Can u plz tell me about ur LNA efficiency,it is working or not.and how much freq. we can give to its input.i hv to design LNA for operating 800Mhz.plz tell me