PLL shows unwanted signal with VCO disconnected
I have designed a frequency synthesizer to generate a Local oscillator at 428.925MHz.
So far I have been unsuccessful generating 428.925MHz.
As part of my testing I programmed the PLL to output the "R" divider output on the test pin. Everything was as expected, a pulse with a period corresponding to the comparison frequency.
I then programmed the PLL to output the "N" divider output. Unexpectantly a pulse appeared with a period far greater than the comparison frequency.
I disabled the VCO and all other circuitry other than the PLL and CPU (3.686MHz crystal). Still the unwanted signal appears. I calculated the original undivided signal as being around the 2.4GHz mark.
Does anyone have any ideas I can try. The PLL is Nationals LMx2346. With the VCO disabled I would expect to see nothing from the "N" divider output. All I can think of is that the PLL is stuffed or receiving mobile phone signals.
A couple ideas, those things can be difficult to get the programming correct. It is easy to get one bit wrong, or send the lsb and the msb, etc. Download the programming software that National has, type in the N and R values that you want, and see what the software says the registers should be programmed with. Compare that to what you are actually sending.
The other possibility is that you are programming a N value that is not allowed. There are values that the counter N can not be programmed to. Once again, the national software usually predicts those.
Finally, you could have the input of the chip free-oscillate if there is not input RF signal, so I would only trust what I saw on the test pin when both the clock and the RF input are applied.
Rich
Most probably you are seeing the self oscillating frequency of the prescaler.
As it is a feedback divider, it is unstable if no signal is injected at its input (I saw this effect a lot of time).
Usually these dividers oscillate to their max divide freq (2.4GHz), that is compatible with the spec of the PLL you are using (2GHz).
Try to short Fin and FinB in this test and see if it disappears (not guaranteed).
I hope it can help.
Mazz
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