What can cause PLL frequency drift?
does frequency stability of a pll output is exactly the same as frequency stability of its reference?
i mean a pll with ref. 10MHz with stability 1ppm and output 100MHz will have 100Hz drift or some other causes will affect on out put drift?
thanks,
Hello,
A PLL controls the VCO based on phase relation between the reference and the VCO. It tries to keep the phase between the two signals constant (for example 0 or 90 degrees).
So if, after some time the phase difference between the reference frequency and Fvco/n is still the same, the frequency must be the same also (otherwise the phase vector of the signal with highest frequency will overrun the other one). So basically, there is no frequency drift between the VCO and n*Freference.
As in all systems, there is noise. The noise introduces a noise component on the phase difference between the two signals, hence also a noise like frequency difference, but the mean value is zero, so over the long time, frequencies are the same.
Looking to your actual problem when the reference have 1ppm frequency drift over time, your output frequency will have the same 1ppm drift.
You have one of two problems:
1) the reference is actually drifiting much more than 1 ppm. The specs for a crystal oscillator are cumulative. So if the power supply droops, and the unit ages, and the temperature rises, you have x + y + z = total drift, i.e. three different specs add up for the worst case tolerance.
2) you are not really phase locked, and need to debug the loop. The first thing would be to look at the VCO tuning voltage, and see if it is near a power supply rail or not looking stable, etc.
For my opinion, an additional dynamic error may occur due to the error signal (VCO control voltage) which not always really is constant - dependent on the kind of loop filter (with/without a zero at s=0).
That is true if he is hopping the frequency quickly.